Making DRAM Available Again: Safely Mitigating RowHammer at Low Performance and Energy Overheads in Modern DRAM-based Systems
Dr. Giray Yağlıkçı
Pstdoctoral Researcher and Lecturer
ETH Zürich
Abstract: Read disturbance in modern DRAM is an important robustness (security, safety, and reliability) problem, where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in other physically nearby DRAM rows. To make matters worse, shrinking technology node size exacerbates DRAM read disturbance at the circuit level over generations. Worsening DRAM read disturbance leads to data integrity issues, and existing read disturbance mitigations greatly reduce the availability of DRAM chips. In this talk, I will cover two of our recent works: Chronus and BreakHammer, tackling data integrity issues caused by DRAM read disturbance at low overhead on DRAM chips’ availability. Chronus is an in-DRAM RowHammer mitigation mechanism, proposing a better implementation of the RowHammer mitigation approach in the latest DDR5 specs, PRAC. Chronus identifies two major shortcomings of PRAC and addresses them via leveraging subarray-level parallelism and dynamically increasing the refresh count when needed. Our evaluation shows that Chronus significantly reduces PRAC’s performance and energy overheads, and achieves near-zero performance overhead for modern DRAM chips, outperforming three variants of PRAC and three other state-of-the-art read disturbance solutions. To aid future research, we open-source our Chronus implementation at https://github.com/CMU-SAFARI/Chronus. BreakHammer is a throttling mechanism that works with existing RowHammer mitigation mechanisms and reduces the number of RowHammer-preventive actions they need to perform. To achieve this, BreakHammer identifies the hardware threads that abnormally trigger many RowHammer-preventive actions, and reduces their memory bandwidth usage via reducing the number of cache miss registers that they can allocate at the last-level cache. By doing so, BreakHammer reduces the memory traffic created by malicious threads, resulting in higher system throughput, fairness, and energy efficiency. BreakHammer has a simplistic implementation in the memory controller with near-zero area overhead. To foster further research, we open-source our BreakHammer implementation and scripts at https://github.com/CMU-SAFARI/BreakHammer.
Bio: Giray is a tenure-track faculty at CISPA and looking forward to hiring young researchers at various levels. His broader research interests span high-performance, energy-efficient, and secure computer architectures aiming robustly and sustainably scalable systems. His research is published in major venues, including HPCA, MICRO, DSN, ISCA, and USENIX Security. Giray received his PhD from ETH Zurich, SAFARI Research Group, in 2024, advised by Professor Onur Mutlu. Giray’s PhD research builds 1) a detailed understanding of DRAM read disturbance, a major limitation of main memory density scaling, and 2) mechanisms that efficiently and scalably mitigate DRAM read disturbance. His PhD dissertation was awarded with ACM SIGMICRO Dissertation Award and William C. Carter PhD Dissertation Award in Dependability in 2025 and received an honorable mention by ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award. Giray’s PhD research is in part 1) supported by Google Security and Privacy Research Award and Microsoft Swiss Joint Research Center and 2) recognized by ETH Medal (nominated), Intel Hardware Security Academic Award 2022 (chosen as a finalist), and ACM PACT Student Research Competition 2023 (won the first place).
DATE: January 07, Wednesday @ 13:30
Place: EA 409
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